Selective material removal refers to being able to remove one material preferentially over another by means of a material removal technique when these materials are subjected to the same material removing environment. Even though there are various material removal techniques, etching is one of the most commonly known and used technique in industry including semiconductor industry.
In semiconductor industry, etching oxide selective to nitride is required for various purposes, including etching contact holes through the oxide selective to nitride spacers and/or nitride gate cap to form a contact to source and drain regions of the transistor. For these purposes, state of the art etching of oxide selective to nitride, including contact etching, is carried out in a dry etch plasma reactor using a gas mixture comprising carbon-fluor-hydrogen based gases such as C4F6, C4F8, CF4, CH2F2 or mixtures thereof.
Selectivity is a key parameter when referring to selective removal of a material over another. One of the mechanisms of achieving selectivity is the selective formation of an etch-inhibiting layer on one of the materials, while the other material is further being etched. When gas mixtures comprising above-mentioned carbon-fluor-hydrogen based gases are used to selectivity etch oxide with respect to silicon nitride, usually this mechanism occurs. A blocking polymer layer is formed on the silicon nitride inhibiting further etching thereof, while oxide is being etched until the desired depth into the oxide is reached. About 5 nm to 10 nm of the silicon nitride will be consumed before such an etch inhibiting layer can be built up. However, such a high consumption of silicon nitride cannot be tolerated for contact etching, where the nitride of the sidewalls spacer and/or gate cap is deemed to be consumed, especially in the processing of advanced technology nodes. Such a consumption of the nitride of the sidewalls spacer and/or nitride cap leads exposure of the gate electrode resulting in an electrical shorting of the gate electrode with the source or the drain region after establishing the electrical contact.
A possible solution to cope with this problem has been disclosed in U.S. Pat. No. 6,331,495 B1. The gate stacks are wrapped by a bi-layer consisting of a first layer of un-doped SiO2, over which a second bread-loafed layer of SiO2 or nitride is deposited. Such a solution is feasible for higher technology nodes, where the gate pitch is on the order of 60 nm or higher. However, as technology nodes are getting smaller following CMOS scaling in accordance with Moore's law, gate pitch is also shrinking to about 60 nm or lower for 10 nanometer technology node or and smaller nodes. This means that such a bread-loafed profile poses the risk of having merged corners, thus jeopardizing or putting extra undesired challenges to the contact etch process.
There is, therefore, a need in the art to remove oxide selective to nitride using a method such that a viable contact etch process can be achieved independent of the technology node, even for technology nodes equal to or smaller than the 10 nanometer technology node in the semiconductor industry.